1. Field of the Invention
The present invention relates to an integrated circuit device wherein an initial state can be set at assembly time and the initial state is set by bonding wires, furthermore, it relates to a microprocessor capable of settling an effective bit width of a data bus and changing the effective data-bus width by instructions.
2. Description of Related Art
Conventionally, in a system using a microprocessor, a method of using external pins for programming by hardware to set an internal state of the microprocessor without using software is used.
For example, in the microprocessor which accesses the external data bus to which peripheral devices of different data bus sizes are connected, a width of data bus must be switched to 8 bits, 16 bits, 32 bits etc. by reasons of a memory or I/O sides to access the external devices. As a means for switching the data bus width, a method called a dynamic bus sizing is known.
In the method of dynamic bus sizing, a signal specifying how many bytes is the memory or I/O device data width which is now addressed, is returned to the microprocessor from the memory side when returning acknowledge to the data strobe at read/write of the memory.
As an example of the conventional microprocessor adopting the method of dynamic bus sizing, a microprocessor MC68020 by Motorola Corp. is known.
In the following the microprocessor MC68020 by Motorola Corp. is described as the prior art.
FIG. 1 is a schematic view showing a configuration of a bus interface of the microprocessor MC68020.
The bus interface of the microprocessor MC68020 comprises, an address bus 51 having the 32-bit width of A0 to A31 bit, a data bus 52 having the 32-bit width of D0 to D31 bit, a sequence control line and signal lines for interruption, arbitration control and so on.
The bus interface of the microprocessor MC68020 is capable of sending and receiving data by adjusting the bus width to the bus ports of 8-bit, 16-bit and 32-bit widths. However, for the purpose of dynamically interfacing with the bus having the bit width which differs in each bus cycle, informing the data size mutually with the outside by two size pins (SIZ1, SIZ0) and 2 sized data acknowledge pins (DSACK1, DSACK0).
A bit width of the operand requested by the microprocessor MC68020 is informed to all of the devices connected to the bus, by using the size pins (SIZ1, SIZ0).
Here, the 2-bit SIZ signal represents, ##EQU1##
The memory, when addressed adequately, informs the bit width of the operand transferred actually from the address to the microprocessor MC68020 by using the sized data acknowledge pins (DSACK1, DSACK0).
Here, the 2-bit DSACK signal represents, ##EQU2##
Relationship between the DSACK signal and SIZ signal is shown in the following.
i) The address (A0 to A31) of the memory which is requested by the microprocessor MC68O20 to be transferred and the SIZ signal of the number of requested bytes are outputted, and simultaneously, a direction of transfer is indicated by the read/write (R/W) signal.
ii) Next, an address strobe signal AS is turned to the low activity to indicate that various signals for data transfer are stabilized.
iii) A memory block and I/O block specified by the address and function code perform the following works.
It is decoded by contents of the addresses A1, A0 that which memory is to be accessed, and it is set by the SIZ signal that how many bytes are to be accessed.
In the case of 2-byte memory width (DSACK=LH), when the SIZ signal indicates one byte, depending on the address A0 which is "1" or "0" (even address or odd address), it is necessary to respond to address which is only for the high order byte or only for the low order byte. In this case, control of offset in memory words when accessing is classified into eight kinds as shown in a schematic view of FIG. 2. At this time, the DSACK signal is returned to the microprocessor in 2 bytes in any case.
When the 4-byte memory width is indicated (DSACK=LL), though fairly complicated control is necessary on the memory side, its state is shown in a schematic view of FIG. 3.
As shown in FIG. 3, in all cases, the off-set in the memory words is decided by the address signals A0, Al, and from the off-set position decided, how many bytes are to be actually accessed by the SIZ signal must be decided.
A decoding function of the size signals SIZ1, SIZ0 and the address signals A0, A1 must be, basically, included in each memory block and I/O block.
Details of the method of dynamic bus sizing of the microprocessor MC68020 is described in page number 5-2 of MOTOROLA "MC68020 32-Bit Microprocessor User's Manual".
As the conventional microprocessor is constructed as aforementioned, external pins for outputting the signal indicating the data width of operand request from the microprocessor to the peripheral devices, and external pins for receiving the signal indicating the operand width transferred from the peripheral devices to the microprocessor are necessary.
Furthermore, external circuits for decoding relationship between the signal indicating the data width of operand request and the address are required respectively on each memory block and I/O block.